PRESCALE=PRESCALE_0, RT=RT_0, UT=UT_0, REBL=REBL_0
SDRAM control register 3
| REN | Refresh enable |
| REBL | Refresh burst length 0 (REBL_0): 1 1 (REBL_1): 2 2 (REBL_2): 3 3 (REBL_3): 4 4 (REBL_4): 5 5 (REBL_5): 6 6 (REBL_6): 7 7 (REBL_7): 8 |
| PRESCALE | Prescaler timer period 0 (PRESCALE_0): 256*16 clock cycles 1 (PRESCALE_1): PRESCALE*16 clock cycles 2 (PRESCALE_2): PRESCALE*16 clock cycles 3 (PRESCALE_3): PRESCALE*16 clock cycles 4 (PRESCALE_4): PRESCALE*16 clock cycles 5 (PRESCALE_5): PRESCALE*16 clock cycles 6 (PRESCALE_6): PRESCALE*16 clock cycles 7 (PRESCALE_7): PRESCALE*16 clock cycles 8 (PRESCALE_8): PRESCALE*16 clock cycles 9 (PRESCALE_9): PRESCALE*16 clock cycles |
| RT | Refresh timer period 0 (RT_0): 256*Prescaler period 1 (RT_1): RT*Prescaler period 2 (RT_2): RT*Prescaler period 3 (RT_3): RT*Prescaler period 4 (RT_4): RT*Prescaler period 5 (RT_5): RT*Prescaler period 6 (RT_6): RT*Prescaler period 7 (RT_7): RT*Prescaler period 8 (RT_8): RT*Prescaler period 9 (RT_9): RT*Prescaler period |
| UT | Refresh urgent threshold 0 (UT_0): 256*Prescaler period 1 (UT_1): UT*Prescaler period 2 (UT_2): UT*Prescaler period 3 (UT_3): UT*Prescaler period 4 (UT_4): UT*Prescaler period 5 (UT_5): UT*Prescaler period 6 (UT_6): UT*Prescaler period 7 (UT_7): UT*Prescaler period 8 (UT_8): UT*Prescaler period 9 (UT_9): UT*Prescaler period |